1. Field of the Invention
This invention relates to an improved demodulator for use in communication systems employing a phase modulated carrier. More particularly, the invention relates to a demodulator having improved apparatus for generating reference vectors, carrier detection signals, and bit synchronization parameters.
2. Description of the Prior Art
Coherent phase shift keyed (CPSK) digital modulation techniques are known to be especially suitable for electric utility power line carrier communication systems. The basic task of such systems is to transmit information over the primary and secondary distribution conductors between a central utility location and customer locations. The information may consist of remote meter reading commands, metering data, load shed commands, load status information, and various other types of data that are useful in automated distribution systems.
The data is converted, at the transmitting end, to strings of binary data bits in a predetermined message format. The information, when converted to digital form, is referred to as baseband data.
In order to transmit the message from the source to the destination, the baseband data is modulated onto a carrier signal by causing the phase of the carrier to assume any of a plurality of predetermined relative phases according to the logic state of the applied baseband data. The modulated carrier signal is then coupled to the power line conductor and propagated to the destination.
A power line communication system employing coherent phase shift keyed modulation is described in U.S. Pat. No. 4,311,964 issued on Jan. 19, 1982 to John R. Boykin. In the transmitter of U.S. Pat. No. 4,311,964, the bipolar data bits are phase encoded onto the carrier with identical bit intervals, or data symbol times, defining a predetermined data rate and are synchronized with the carrier signal so as to be integrally related to the carrier signal frequency.
The system described in the aforementioned U.S. Pat. No. 4,311,964 utilizes a phase reversal keying, such that the phase of the carrier is caused to assume either of two phase states separated by 180.degree., according to whether the baseband digital data modulated thereon is a logic 1 or a logic 0. In the receiving apparatus disclosed therein, the modulated carrier is hard limited to produce square wave carrier signals. The polarity of the hard limited carrier signals, divided into segments, is then sampled at a sampling pulse rate selected such that the ratio of the sampling rate to the carrier frequency is not an integer. The sampling process enables the demodulator to determine the relative position of the zero crossings of the square wave carrier signal. This information is used to generate a phase angle vector signal representative of the phase state of the present segment of the incoming carrier signal relative to a coordinate system generated internally within the demodulator.
The phase angle vector signal is used to generate a reference vector signal. The phase angle vector and reference vector signals are then applied to a phase detector to yield a signal output which indicates which of the allowable phase states has been assumed by a given segment of the incoming carrier signal. This phase information is then utilized to reconstruct the baseband digital data originally supplied to the transmitter. This prior art apparatus produces the reference vector signal by generating an intermediate vector signal at a frequency twice that of the incoming carrier signal. This intermediate vector signal, known as a double frequency vector, is then digitally integrated over an extended period of time to produce a reference vector signal. The reference vector and phase angle vector signals are then applied to a phase detector which produces a signal output indicating whether the incoming carrier signal has assumed the nominal phase or the reversed phase to in turn indicate whether the baseband digital data is a logic `or logic 0. Thus, if the phase angle vector signal derived from the incoming carrier is determined to be 45.degree. relative to the internally generated coordinate system, and is followed by a phase angle vector signal having a phase of 225.degree. (indicating a phase reversal, or change of the baseband digital data from a logic 1 to a logic 0), the phase of the intermediate vector signal generated at twice the frequency of the incoming carrier signal is 45.degree. for both of the aforementioned phase angle vector signals. This system provides generally satisfactory service, but is rather complex. Furthermore, in some circumstances the system may not exhibit sufficient noise immunity and may become subject to unnecessary drop-out of the carrier detect signal.
In prior art digital demodulators such as described in the aforementioned U.S. Pat. No. 4,311,964 employing sampling techniques for systems with a data transmission rate much lower than the carrier frequency, bit framing is required, since each baseband data symbol, or bit, extends over several carrier segments. A data symbol extends over four segments in the apparatus of U.S. Pat. No. 4,311,964. It is necessary to determine at which carrier segment a data symbol begins. For example, is the carrier segment currently being processed actually the first segment of a new data symbol (which will also include the next three segments), is it the last segment of a data symbol also including the three preceding segments, or is it a middle segment of a data symbol which also extends over one or two preceding and succeeding segments. The process of bit framing, or synchronizing, was done only after the successful detection of a carrier signal by the receiver of U.S. Pat. No. 4,311,964. Carrier detection therefore was required to occur early enough to insure that successful bit framing would be accomplished during the transmission of the message preamble. Furthermore, the serial execution of the carrier detection and bit framing functions causes duplication of calculations which may allow significant error propagation due to the limited precision of 8-bit arithmetic used in some prior art microprocessor based systems. It would be desirable to provide demodulator apparatus and methods to enable concurrent bit framing and carrier detection.